Erasable programmable read-only memory (EPROM) devices are usually fabricated by employing metal-oxide-semiconductor (MOS) transistors with a double-layer polysilicon gate structure as the memory cells in a memory cell array. The first polysilicon gate of the MOS transistor is completely insulated from any outside connection and is called a "floating gate". Information can be programmed in the memory array by avalanche injection of charge carriers into the floating gate through a thin insulation layer from the substrate. The memory cell is thus called a floating gate avalanche injection MOS (FAMOS) device. Since the floating gate is surrounded by an insulation layer, the charges, once trapped, stay inside the floating gate during normal storage and operation conditions. The erasure of information from an EPROM device is accomplished by exposing the device to ultraviolet light with high enough energy to excite the stored charges to escape from the floating gates. After the information stored on all memory cells is completely purged, new information can be written electrically into the array.
Like other ROMs, EPROMs include, beside an array of memory cells, addressing circuitry with peripheral transistors for providing access to specific memory cells so as to enable the contents of the memory cells to be read out or written. Some of the peripheral transistors, such as those controlling programming, may be required to have a high breakdown voltage, while others, used only for reading data and operating at normal signal voltages, have lower breakdown voltages.
In order to program an EPROM efficiently, it is necessary to produce a large electric field near the drain junction under the gates of specific FAMOS devices for charge generation and injection. An electric field is achieved by applying a high voltage to the gate and the drain of the FAMOS device. Because of the high voltage applied when programming an EPROM, the isolation field area must have a high enough threshold voltage to prevent two adjacent active devices from shorting. This high field threshold voltage is usually achieved by a higher field implant dose which results in higher parasitic capacitance and slower device characteristics. Unless a separated field implant mask and a lower dose of field implant are applied to the devices in the speed path, these devices will have a similar higher parasitic capacitance and slower device characteristics. It then results in a slower product speed.
It is an object of the present invention to provide a process of fabricating EPROMs having higher speed and performance characteristics.